Browse > Home / Electrical Engineering, Engineering Jobs, Mid Level / Design Verification Engineer in Austin, TX

Design Verification Engineer in Austin, TX

February 18, 2008

Job Title : Design Verification Engineer
Job Location : Austin, TX
Career Level : Mid (5-10 yrs)
Job Type : Direct, Contract
Pay Type : Salary
Maximum Pay : $95,000
Minimum Pay : $80,000
Required Engineering Major/Field : Electrical

Required Skills : Requires a BSEE or BSCS and 5 years of verification experience, preferably in mixed signal products. The main requirement is a strong background in Verilog, with experience in digital and mixed signal verification. The candidate must have strong scripting skills in Perl, Unix/Linux shell, TCL, and must be able to write and debug analog behavioral models in both Verilog, SystemVerilog, and VerilogA. Knowledge of Verilog Assertions is also a plus. The proven ability to create, evaluate, debug, and improve a verification process is essential for this position.

General Job Description : Responsible for developing, maintaining, and verifying mixed-signal designs for audio data converters. Detailed responsibilities include functional verification, testbench generation, coverage analysis, regression management, test vector creation, and development of verification plans for various devices. Candidate must work closely with applications and chip design groups to support both pre-silicon verification and post silicon validation efforts.

Application Instructions :

Please email resume to shawnda [at] siliconelite [dot] com in Word format.

Contact Name : Shawnda Ewing
Contact Email : shawnda [at] siliconelite [dot] com

[?]

Written by bradley · Filed Under Electrical Engineering, Engineering Jobs, Mid Level 

Comments